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MIC2589/2595
Micrel
MIC2589/MIC2595
Single-Channel, Negative High-Voltage Hot Swap Power Controllers/Sequencers
General Description
The MIC2589 and MIC2595 are single-channel, negativevoltage hot swap controllers designed to address the need for safe insertion and removal of circuit boards into "live" system backplanes, while using few external components. The MIC2589/89R and the MIC2595/95R are each available in 14-pin SOIC packaging and work in conjunction with an external N-Channel MOSFET for which the gate drive is controlled to provide inrush current limiting and output voltage slew-rate control. Overcurrent fault protection is also provided for which the overcurrent threshold and the overcurrent duration are programmable. Very fast fault response is provided to ensure that system power supplies maintain regulation even during output short circuits. This family offers two responses to a circuit breaker fault condition: the MIC2589 and MIC2595 latch the circuit breaker's output off if the overcurrent threshold interval is exceeded while the MIC2589R and MIC2595R automatically attempt to restart at a fixed duty cycle after a current limit fault. A primary Power-Good signal and two secondary (delayed and staggered) Power-Good signals are provided to indicate that the output voltage of the inrush current limiter is within its valid operating range. These signals can be used to perform an allat-once or a sequenced enabling of one or more DC-DC power modules. All support documentation can be found on Micrel's web site at www.micrel.com.
Features
* Provides safe insertion and removal from live -48V (nominal) backplanes * Operates from -19V to -80V * Fast responding circuit breaker (<1s) to short circuit conditions * User-programmable overcurrent detector response time * Electronic circuit breaker function: Output latch OFF (MIC2589/95) or Output auto-retry (MIC2589R/95R) * Active current regulation precisely controls inrush currents * Regulated maximum output currents into faults * Programmable undervoltage and overvoltage lockouts (MIC2589/89R) * Programmable UVLO hysteresis (MIC2595/95R) * Staggered `Power-Good' outputs provide load sequencing * Fault reporting: Active-HIGH (MIC25XX-1) and Active-LOW (MIC25XX-2) Power-Good signal output
Applications
* Central office switching * -48V power distribution * Distributed power systems
Typical Application
-48V RETURN (Long Pin) -48V RETURN (Short Pin) R1 698k 1% R2 11.8k 1%
4
DC-DC Converter IN+ OUT 100F MIC2589-1BM MIC2589R-1BM
14
+2.5V
/ON/OFF IN- PWRGD1 PWRGD2
1 12 13 2
GND
+2.5V RETURN
VDD
3
UV
PWRGD3 PGTIMER CFILTER
DC-DC Converter IN+ OUT 100F /ON/OFF IN- GND
+3.3V
5 6
OV VEE
7
CNLD SENSE
9
+3.3V RETURN
R3 12.4k 1%
GATE
10
DRAIN
11
CFILTER CNLD
CPG DC-DC Converter IN+ OUT 100F /ON/OFF IN- GND Input Overvoltage = 71.2V Input Undervoltage = 36.5V (See "Functional Description" for more detail)
R4 0
CGATE M1
+5V
-48V INPUT (Long Pin)
+5V RETURN
RSENSE
Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com
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Ordering Information
Part Number MIC2589-1BM MIC2589-2BM MIC2589R-1BM MIC2589R-2BM MIC2595-1BM MIC2595-2BM MIC2595R-1BM MIC2595R-2BM PWRGD Polarity Active-High Active-Low Active-High Active-Low Active-High Active-Low Active-High Active-Low Input Voltage Monitor Pins Programmable UVLO & OVLO Programmable UVLO & OVLO Programmable UVLO & OVLO Programmable UVLO & OVLO Programmable UVLO Hysteresis Programmable UVLO Hysteresis Programmable UVLO Hysteresis Programmable UVLO Hysteresis Circuit Breaker Function Latched Off Latched Off Auto-Retry Auto-Retry Latched Off Latched Off Auto-Retry Auto-Retry Package 14-pin SOIC 14-pin SOIC 14-pin SOIC 14-pin SOIC 14-pin SOIC 14-pin SOIC 14 pin SOIC 14-pin SOIC
Pin Configuration
PWRGD1 1 PGTIMER 2 UV 3 OV 4 CFILTER 5 CNLD 6 VEE 7 14 VDD 13 PWRGD3 12 PWRGD2 11 DRAIN 10 GATE 9 SENSE 8 NC /PWRGD1 1 PGTIMER 2 UV 3 OV 4 CFILTER 5 CNLD 6 VEE 7 14 VDD 13 /PWRGD3 12 /PWRGD2 11 DRAIN 10 GATE 9 SENSE 8 NC
14-Pin SOIC (M) MIC2589-1BM MIC2589R-1BM
14-Pin SOIC (M) MIC2589-2BM MIC2589R-2BM
PWRGD1 1 PGTIMER 2 OFF 3 ON 4 CFILTER 5 CNLD 6 VEE 7
14 VDD 13 PWRGD3 12 PWRGD2 11 DRAIN 10 GATE 9 SENSE 8 NC
/PWRGD1 1 PGTIMER 2 OFF 3 ON 4 CFILTER 5 CNLD 6 VEE 7
14 VDD 13 /PWRGD3 12 /PWRGD2 11 DRAIN 10 GATE 9 SENSE 8 NC
14-Pin SOIC (M) MIC2595-1BM MIC2595R-1BM
14-Pin SOIC (M) MIC2595-2BM MIC2595R-2BM
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Pin Description
Pin Number Pin Name PWRGD1 (MIC25XX-1) Active-High 1 /PWRGD1 (MIC25XX-2) Active-Low 2 PGTIMER Pin Function Power-Good Output 1: Asserted when the voltage on the DRAIN pin (VDRAIN) is within VPGTH of VEE, indicating that the output voltage is within proper specifications. For the MIC2589-1 and MIC2985-1, PWRGD1 will be high impedance when VDRAIN is less than VPGTH, and will pull-down to VDRAIN when VDRAIN is greater than VPGTH. For the MIC2589-2 and MIC2595-2, /PWRGD1 will pull-down to VDRAIN when VDRAIN is less than VPGTH, and will be high-impedance when VDRAIN is greater than VPGTH. A capacitor connected from this pin to VEE sets the time interval between assertions of PWRGD2 (or /PWRGD2) and PWRGD3 (or /PWRGD3) relative to PWRGD1 (or /PWRGD1). See the "Functional Description" for further detail. MIC2589 and MIC2589R: Undervoltage Threshold Input. When the voltage at the UV pin is less than the VUVL threshold, the GATE pin is immediately pulled low by an internal 100A current pull-down. The UV pin is also used to cycle the device off and on to reset the circuit breaker. Taken together, the OV and UV pins form a window comparator which define the limits of VEE within which the load may safely be powered. MIC2595 and MIC2595R: Turn-Off Threshold. When the voltage at the OFF pin is less than the VOFFL threshold, the GATE pin is immediately pulled low by an internal 100A current pull-down. The OFF pin is also used to cycle the device off and on to reset the circuit breaker. Taken together, the ON and OFF pins provide programmable hysteresis for the MIC2595 to be enabled. MIC2589 and MIC2589R: Overvoltage Threshold Input. When the voltage at the OV pin is greater than the VOVH threshold, the GATE pin is immediately pulled low by an internal 100A current pull-down. MIC2595 and MIC2595R: Turn-On Threshold. At initial system power-up or after the part has been shut off by the OFF pin, the voltage on the ON pin must be above the VONH threshold in order for the MIC2595 to be enabled. Current Limit Response Timer: A capacitor connected between this pin and VEE provides filtering against nuisance tripping of the circuit breaker by setting a time delay, tFLT, for which an overcurrent event must last prior to signaling a fault condition and latching the output off. The minimum time for tFLT will be the time it takes for the output (capacitance) to charge to VEE during start-up. This pin is held to VEE with a 3A current pull-down when no current limit condition exists. See the "Functional Description" for further details. No-Load Detect Timer: A capacitor between this pin and VEE sets the interval, tNLD, for which the current through the external MOSFET can drop below 10% of full-scale current limit before the circuit breaker is tripped. Tying this pin to VEE will disable this function. This pin is held to VEE by an internal NMOS when there is no undercurrent condition. Negative Supply Voltage Input. No Internal Connection. Circuit Breaker Sense Input: A resistor between this pin and VEE sets the current limit trip point for the circuit. When the current limit threshold of IR = 50mV is exceeded for tFLT, the circuit breaker is tripped and the GATE pin is immediately pulled low. Toggling UV or OV will reset the circuit breaker. To disable the circuit breaker, externally tie SENSE and VEE can be connected together. Gate Drive Output: Connects to the Gate of an N-Channel MOSFET. Drain Sense Input: Connects to the Drain of an N-Channel MOSFET.

3
UV Threshold
3
OFF (Turn-Off Threshold)
4
OV Threshold ON (Turn-On Threshold) CFILTER

4
5
6
CNLD
7 8 9
VEE NC SENSE
10 11
GATE DRAIN
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Pin Number 12
Pin Name PWRGD2 (MIC2589-1) (MIC2595-1)
Pin Function Power-Good Output 2: Asserted when the following is true: (PWRGD1 = Asserted) AND (Time after Assertion of PWRGD1 = Time PWRGD2, as programmed by the capacitor on PGTIMER). Once PWRGD1 is asserted, the PGTIMER pin begins to change and PWRGD2 will assert when PGTIMER crosses the PWRGD2 threshold (VTHRESH(PG2) = 0.63V, typical). Also see PWRGD1 and PGTIMER pin descriptions. /Power-Good Output 2: Asserted when the following is true: (/PWRGD1 = Asserted) AND (Time after Assertion of /PWRGD1 = Time /PWRGD2, as programmed by the capacitor on PGTIMER). Once /PWRGD1 is asserted, the PGTIMER pin begins to change and /PWRGD2 will assert when PGTIMER crosses the /PWRGD2 threshold (VTHRESH(PG2) = 0.63V, typical). Also see /PWRGD1 and PGTIMER pin descriptions. Power-Good Output 3: Asserted when the following is true: (PWRGD1 = Asserted) AND (Time after Assertion of PWRGD1 = Time PWRGD3, as programmed by the capacitor on PGTIMER). Once PWRGD1 is asserted, the PGTIMER pin begins to change and PWRGD3 will assert when PGTIMER crosses the PWRGD3 threshold (VTHRESH(PG3) = 1.15V, typical). Also see PWRGD1 and PGTIMER pin descriptions. /Power-Good Output 3: Open Collector. Asserted when the following is true: (/PWRGD1 = Asserted) AND (Time after Assertion of /PWRGD1 = Time /PWRGD3, as programmed by the capacitor on PGTIMER). Once /PWRGD1 is asserted, the PGTIMER pin begins to change and /PWRGD3 will assert when PGTIMER crosses the /PWRGD3 threshold (VTHRESH(PG3) = 1.15V, typical). Also see /PWRGD1 and PGTIMER pin descriptions. Positive Supply Input.

12
/PWRGD2 (MIC2589-2) (MIC2595-2)
13
PWRGD3 (MIC2589-1) (MIC2595-1)
13
/PWRGD3 (MIC2589-2) (MIC2595-2)
14
VDD
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Absolute Maximum Ratings(1)
(All voltages are referred to VEE) Supply Voltage (VDD - VEE) ......................... -0.3V to 100V DRAIN, PWRGD pins ................................... -0.3V to 100V GATE pin ..................................................... -0.3V to 12.5V SENSE, OV, UV, ON, OFF pins ....................... -0.3V to 6V ESD Ratings(3) .............................................................................. 2kV Soldering Vapor Phase .......................... (60 sec.) +220C +5 0C Infrared ................................... (15 sec.) +235C +5 0C
Operating Ratings(2)
Supply Voltage (VDD-VEE) ............................. +19V to +80V Ambient Temperature Range (TA) ............... -40C to 85C Junction Temperature (TJ) ........................................ 125C Package Thermal Resistance SOIC (JA) ......................................................... 120C/W
DC Electrical Characteristics(4)
VDD = 48V, VEE = 0V, TA = 25C, unless otherwise noted. Bold indicates specifications apply over the full operating temperature range of -40C to 85C. Symbol VDD - VEE IDD VTRIP INLDTH Parameter Supply Voltage Supply Current Circuit Breaker Trip Voltage No-Load Detect Threshold VTRIP = VSENSE - VEE % of full-scale current limit IOUT decreasing IOUT increasing 1.17 Note 5 15V (VDD - VEE) 80V VGATE = VEE to 8V 19V (VDD - VEE) 80V VSENSE = 50mV (VSENSE - VEE) = 100mV VGATE = 2V (VSENSE - VEE) > VTRIP VCFILTER = 0.75V VGATE = 3V (VSENSE - VEE) < VTRIP VCFILTER = 0.75V VGATE = 3V (VSENSE - VEE) > VTRIP 100 65 10 9 30 40 Condition Min 19 4 50 20 22 2 1.24 25 10 45 0.2 240 95 135 1.33 40 11 60 Typ Max 80 6 60 mA mV % % % V A V A A mA A Units
INLDHYS VCNLD ICNLD VGATE IGATEON ISENSE IGATEOFF ICFILTER
No-Load Detect Threshold Hysteresis % of full-scale current limit No-Load Detect Timer High Threshold Voltage No-Load Detect Timer Capacitor Charge Current GATE Drive Voltage, (VGATE - VEE) GATE Pin Pull-Up Current SENSE Pin Current GATE Pin Sink Current CFILTER Charge Current
CFILTER Pull-Down Current
2
4
6
A
VCFILTER(TRIP) High Threshold Voltage Overcurrent Detect Timer VCFILTER(RETRY) Voltage on CFILTER to Trigger Auto-Retry (MIC2589R and MIC2595R only) IPGTIMER
Notes:
1.17 0.17
1.25 0.22 45
1.33 0.25 80
V V A
PGTIMER Charge Current
Voltage on PGTIMER = 0.75 V
30
1. Exceeding the "Absolute Maximum Ratings" may damage the devices. 2. The devices are not guaranteed to function outside the specified Operating Conditions. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model: 1.5k in series with 100pF. Machine model: 200pF, no series resistance. 4. Specification for packaged product only. 5. Not 100% tested. Parameters are guaranteed by design.
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DC Electrical Characteristics(6)
VDD = 48V, VEE = 0V, TA = 25C, unless otherwise noted. Bold indicates specifications apply over the full operating temperature range of -40C to 85C. Symbol Parameter Condition Min 0.5 1.00 Voltage on PGTIMER = 0.5 V Low-to-High transition High-to-Low transition 250 1.198 1.165 Typ 0.63 1.15 500 1.223 1.203 20 High-to-Low transition Low-to-High transition 1.198 1.213 1.223 1.243 20 Low-to-High transition High-to-Low transition VUV = 1.25V High-to-Low Transition (VDRAIN - VEE) 1.1 1.26 1.198 1.198 1.223 1.223 1.247 1.247 0.5 1.40 1.247 1.272 Max 0.8 1.30 750 1.247 1.232 Units V V V V mV V V mV V V A V VTHRESH(PG2) PGTIMER Threshold Voltage for PWRGD2 and /PWRGD2 VTHRESH(PG3) PGTIMER Threshold Voltage for PWRGD3 and /PWRGD3 RPGTIMER VOVH VOVL VOVHYS VUVL VUVH VUVHYS VONH VOFFL ICNTRL VPGTH VOLPG PGTIMER Discharge Resistance OV Pin High Threshold Voltage (MIC2589 and 2589R parts only) OV Pin Low threshold Voltage (MIC2589 and 2589R only) OV Pin Hysteresis (MIC2589 and 2589R only) UV Pin Low threshold Voltage (MIC2589 and 2589R only) UV Pin High Threshold Voltage (MIC2589 and 2589R only) UV Pin Hysteresis (MIC2589 and 2589R only) ON Pin High Threshold Voltage (MIC2595 and 2595R only) OFF Pin Low Threshold Voltage (MIC2595 and 2595R only) Input Current (OV, UV, ON, OFF Pins) Power-Good Threshold
PWRGD Output Voltage VOLPG - VDRAIN (relative to voltage at the DRAIN pin) 0mA IPG(LOW) 1mA MIC25XX-1 MIC25XX-2 (VDRAIN - VEE) > VPGTH (VDRAIN - VEE) < VPGTH VPWRGD = VDD = 80 V -0.25 -0.25 0 0.8 0.8 1 V V A
ILKG(PG)
Note:
PWRGD Output Leakage Current
6. Specification for packaged product only.
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AC Electrical Characteristics(7)
Symbol tOCSENSE tOVPHL tOVPLH tUVPHL tUVPLH tOFFPHL tONPLH tPGLH1 tPGHL1 tPGHL2 tPGLH2
Notes: 7. Specification for packaged product only. 8. Not 100% production tested. Parameters are guaranteed by design.
Parameter Overcurrent Sense to GATE Low Trip Time, Figure 2 OV High to GATE Low, Figure 3 (MIC2589 and 2589R only) OV Low to GATE High, Figure 3 (MIC2589 and 2589R only) UV Low to GATE Low, Figure 4 (MIC2589 and 2589R only) UV High to GATE High, Figure 4 (MIC2589 and 2589R only) OFF Low to GATE Low, Figure 5 (MIC2595 and 2595R only) ON High to GATE High, Figure 5 (MIC2595 and 2595R only) DRAIN Low to PWRGD1 Output High (-1) DRAIN High to all PWRGDx Outputs Low (-1) DRAIN Low to /PWRGD1 Output Low (-2) DRAIN High to all /PWRGDx Outputs High (-2)
Condition VSENSE - VEE = OV = 1.5V(8) OV = 1.0V(8) UV = 1.0V(8) UV = 1.5V(8) OFF = 1.0V(8) ON = 1.5V(8) CLOAD on PWRGDx = 50pF, RPULLUP = 100k(8) CLOAD on PWRGDx = 50pF, RPULLUP = 100k(8) CLOAD on /PWRGDx = 50pF, RPULLUP = 100k(8) CLOAD on /PWRGDx = 50pF, RPULLUP = 100k(8) 100mV(8)
Min
Typ
Max 3.5
Units s s s s s s s s s s s
1 1 1 1 1 1 3 5 5 3
Test Circuit
[Section under construction]
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Timing Diagrams
OVERCURRENT EVENT
t < tFLT ILIMIT ILOAD INLDTH 0A
t tFLT tNLD
Load current is regulated at ILIMIT = 50mV/RSENSE
Output OFF (at VDD)
VDRAIN (at VEE) VUV or VOFF Reduction in VDRAIN to support ILIMIT = 50mV/RSENSE VUVL (VUV -- VEE) (at VEE) VUVH (VUV -- VEE) (at VEE) (at VEE)
Figure 1. Overcurrent and Undercurrent (No Load) Response
100mV VSENSE - VEE tOCSENSE VGATE 1V
Figure 2. SENSE to GATE LOW Timing Response
1.223V VOV tOVPHL VGATE 1V tOVPLH
1.203V
1V
Figure 3. MIC2589/89R Overvoltage Response
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VUV 1.223V tUVPHL VGATE 1V 1V tUVPLH 1.243V
Figure 4. MIC2589/89R Undervoltage Response
VOFF
1.223V
tOFFHL VGATE 1V
Figure 5a. MIC2595/95R OFF to GATE Drive Response
1.223V VON tONLH
VGATE
1V
Figure 5b. MIC2595/95R ON to GATE Drive Response
MIC2589/95-1 VDRAIN VPGTH VEE tPGLH1 PWRGD Outputs PWRGDx not asserted VPWRGD -- VDRAIN = 0V VEE PWRGD1 MIC2589/95-2 VDRAIN VPGTH VEE tPGHL2 /PWRGD Outputs VEE /PWRGD1 /PWRGD2 /PWRGD3 tPGLH2 VPGTH PWRGD2 PWRGD3 tPGHL1 PWRGDx not asserted VPWRGD -- VDRAIN = 0V VPGTH
PWRGDx asserted - High Impedance
Figure 6. DRAIN to Power-Good Response
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Functional Diagram
VDD1 VDD Internal VDD and Reference Generator VDD1 VREF 45A
GATE Error AMP SENSE VEE 50mV VDD1 95A - + VEE VDD1 VEE PWRGD1 PWRGD2 PWRGD3 + VCFILTER - VEE 4A VREF
100A
CFILTER
VEE VDD1 25A
/PWRGD1 /PWRGD2 /PWRGD3 Logic + Circuit Breaker EN
+
VEE 6V Clamp VPGTH VDD1
-
CNLD VCNLD
+ -
- Internal PG +
DRAIN
VEE UV - + VTH(UV/OV) - OV + + - VTH(PG3) + -
45A PGTIMER VTH(PG2)
VEE For Power-Good circuitry only denotes -2 option
MIC2589 Block Diagram
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The Power-Good Output Signals For the MIC2589/95-1 and MIC2589R/95R-1, power-good output signal PWRGD1 will be high impedance when VDRAIN drops below VPGTH, and will pull-down to VDRAIN when VDRAIN is above VPGTH. For the MIC2589/95-2 and the MIC2589R/95R-2, power-good output signal /PWRGD1 will pull down to the potential of the VDRAIN pin when VDRAIN drops below VPGTH and will be high impedance when VDRAIN is above VPGTH. Hence, the -1 parts have an active-high PWRGDX signal and the -2 parts have an active-low /PWRGDX output. PWRGDX (or /PWRGDX) may be used as an enable signal for one or more following DC/DC converter modules or for other system uses as desired. When used as an enable signal, the time necessary for the PWRGD (or /PWRGD) signal to pull-up (when in high impedance state) will depend upon the load (RC) that is present on this output. Power-good output signals PWRGD2 (/PWRGD2) and PWRGD3 (/PWRGD3) follow the assertion of PWRGD1 (/PWRGD1) with a sequencing delay set by an external capacitor (CPG) from the controller's PGTIMER pin (Pin 2) to VEE. An expression for the sequencing delay between PWRGD2 and PWRGD1 is given by:
tPGDLY2 -1 = VTHRESH(PG2) x CPG IPGTIMER
Functional Description
Hot Swap Insertion When circuit boards are inserted into systems carrying live supply voltages ("hot swapped"), high inrush currents often result due to the charging of bulk capacitance that resides across the circuit board's supply pins. These current spikes can cause the system's supply voltages to temporarily go out of regulation causing data loss or system lock-up. In more extreme cases, the transients occurring during a hot swap event may cause permanent damage to connectors or onboard components. The MIC2589 and the MIC2595 are designed to address these issues by limiting the maximum current, which is allowed to flow during hot swap events. This is achieved by implementing a constant-current loop at turn-on. In addition to inrush current control, the MIC2589 and the MIC2595 incorporate input voltage supervisory functions and userprogrammable overcurrent protection, thereby providing robust protection for both the system and the circuit board. Start-Up Cycle When the input voltage is to the IC is between the overvoltage and undervoltage thresholds (MIC2589 and MIC2589R) or is greater than VON (MIC2595 and MIC2595R), a start cycle is initiated. When the IC is enabled, the GATE pin voltage rises from 0V with respect to VEE to approximately 10V above VEE. This 10V gate drive is sufficient to fully enhance commonly available power MOSFETs for the lowest possible DC losses. Capacitor CGATE compensates circuitry internal to the IC, while R4 minimizes the potential for high frequency parasitic oscillations from occurring in M1. The drain current of the MOSFET is regulated to ensure that it never exceeds the programmed threshold, as described in the "Circuit Breaker Function" section. Capacitor CFILTER sets the value of overcurrent detector delay, tFLT, which is the time for which an overcurrent event must last to signal a fault condition and to cause an output latch-off. These devices will be driving a capacitive load in most applications, so a properly chosen value of CFILTER prevents false-, or nuisance-, tripping at turn-on as well as providing immunity to noise spikes after the start-up cycle is complete. The procedure for selecting a value for CFILTER is given in the "Circuit Breaker Function" section. Resistor R4, in series with the power MOSFET's gate, may be required in some layouts to minimize the potential for parasitic oscillations occurring in M1. Note though, that resistance in this device of the circuit has a slight destabilizing effect upon the MIC2589/95's current regulation loop. If possible, use high-frequency PCB layout techniques and use a dummy resistor, such that R4 = 0. If during prototyping an R4 is required, common values for R4 range between 4.7 to 20 for various power MOSFETs.
where VTHRESH(PG2) (= 0.63V, typically) is the PWRGD2 threshold voltage for PGTIMER and IPGTIMER (= 45A, typically) is the internal PGTIMER charge current. Similarly, an expression for the sequencing delay between PWRGD3 and PWRGD2 is given by: tPGDLY3 - 2 =
(V
THRESH(PG3)
- VTHRESH(PG2) x CPG
)
IPGTIMER
where VTHRESH(PG3) (= 1.15V, typically) is the PWRGD3 threshold voltage for PGTIMER. Therefore, power-good output signal PWRGD2 (/PWRGD2) will be delayed after the assertion of PWRGD1 (/PWRGD1) by: tPGDLY2-1 (ms) 14 x CPG(F) ms Power-good output signal PWRGD3 (/PWRGD3) follows the assertion of PWRGD2 by a delay: tPGDLY3-2 (ms) 11.5 x CPG(F) ms For example, for a 10F value for CPG, power-good output signal PWRGD2 will be asserted 140ms after PWRGD1. Power-good signal PWRGD3 will then be asserted 140ms after PWRGD2 and 255ms after the assertion of PWRGD1. The relationships between VDRAIN, VPGTH, PWRGD1, PWRGD2, and PWRGD3 are shown in Figure 6.
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Circuit Breaker Function The MIC2589/89R and the MIC2595/95R employ an electronic circuit breaker that protects the external power MOSFET and other system components against large-scale faults, such as short circuits. The current-limit threshold is set via an external resistor, RSENSE, connected between the VEE and SENSE. For the MIC2589/89R and MIC2595/95R, a timer is set via capacitor CFILTER that determines the length of the time delay (tFLT) for which the device remains in current limit before the circuit breaker is tripped. This programmable delay prevents tripping of the circuit breaker because of high inrush current charging bulk and distributed capacitive loads. Whenever the voltage across RSENSE exceeds 50mV, two things happen: 1. A constant-current regulation loop is engaged which is designed to hold the voltage across RSENSE equal to 50mV. This protects both the load and the MIC2589/95 circuits from excessively high currents. This current-regulation loop will engage in less than 1s from the time at which the overvoltage condition on RSENSE occurs. 2. Capacitor CFILTER is charged up to an internal VCFILTER(TRIP) threshold (= 1.25V) by an internal 95A current source. If the voltage across CFILTER crosses this threshold, the circuit breaker trips and the GATE pin is immediately pulled low by an internal current pull-down. This operation turns off the MOSFET quickly and disconnects the input from the load. The value of CFILTER should be selected to allow the circuit's minimum regulated value of IOUT to equal ITRIP for somewhat longer than the time it takes to charge the total load capacitance. An initial value for CFILTER is found by calculating the time it will take for the MIC2589/95 to completely charge up the output capacitive load. Assuming the load is enabled by the PWRGDX (or /PWRGDX) signal(s) of the IC, the turn-on delay time is derived from the following expression, I = C x (dv/dt):
t TURN-ON = CLOAD x VDD - VEE ILIMIT
Micrel
For example, in a system with a CLOAD = 150F, a maximum (VDD - VEE) = 72V, and a maximum load current on a nominal -48V buss of 1.65A, the nominal circuit design equations steps are: 1. Choose ILIMIT = IHOT_SWAP(nom) = 2A (1.65A + 20%); 38.8mV = 19.4m (closest 1% 2A standard value is 19.6m); 3. Using ICHARGE = ILIMIT = 2A, the application circuit turnon time is calculated: 2. Select an RSENSE =
2A Allowing for capacitor tolerances and a nominal 6ms turn-on time, an initial worst-case value for CFILTER is: CFILTER(WORST-CASE) = 6ms x (115.4 x 10-6F/sec) = 692nF The closest standard 5% tolerance capacitor value is 698nF and would be a good initial starting value for prototyping. Whenever the hot swap controller is not in current limit, CFILTER is discharged to VEE by an internal 4A current source. For the MIC2589R/95R devices, the circuit breaker automatically resets after (20) tFLT time constants (20 x tFLT). If the fault condition still exists, capacitor CFILTER will again be charge up to VFILTER(TRIP) where the circuit breaker is tripped. Capacitor CFILTER will then be discharged by an internal 4A current source until the voltage across C FILTER goes below VFILTER(RETRY), at which time another start cycle is initiated. This will continue until the fault condition is removed or input power is removed/cycled. The duty cycle of the auto-restart function is therefore fixed at 5% and the period of the autorestart cycle is given by:
t AUTO-RESTART = 20 x
t TURN-ON =
(150F x 72V) = 5.4ms (use 6 ms)
(CFILTER ) x (1.25V - 0.22V)
95A
ms = CFILTER x 216.8 F
(
)
Using parametric values specific to the MIC2589/95, an expression relating a design nominal value for CFILTER to the circuit's turn-on delay time is:
CFILTER (nom) =
(t TURN-ON x ICFILTER (typ))
VCFILTER (typ) t TURN-ON x 95A F = = t TURN-ON x 76 x 10 -6 1.25V sec
Substituting the variables above with the specification limits of the MIC2589/95, an expression for the worst-case value for CFILTER is given by:
135A CFILTER (max) = t TURN-ON x 1.17V F = t TURN-ON x 115.4 x 10 -6 sec
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The auto-restart period for the example above where the worst-case CFILTER was determined to be 698nF is: tAUTO-RESTART = 151ms Current Sensing As mentioned before, the MIC2589/89R and the MIC2595/95R use an external, low-value resistor in series with the source of the external MOSFET to measure the current flowing into the load. The VEE connection (Pin 7) to the IC is one input to the device's internal current sensing circuits and the SENSE connection (Pin 9) is the other input. The sense resistor is nominally valued at: RSENSE (nom) = VTRIP (typ) IHOT_SWAP (nom)
where VTRIP(typ) is the nominal circuit breaker threshold voltage (= 50mV) and IHOT_SWAP(nom) is the nominal hot swap load current level to trip the internal circuit breaker in the application. 12 March 2004
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To accommodate worst-case tolerances in the sense resistor (for a 1% initial tolerance, allow 3% tolerance for variations over time and temperature) and circuit breaker threshold voltages, a slightly more detailed calculation must be used to determine the minimum and maximum hot swap load currents. As the MIC2589/95's minimum current-limit threshold voltage is 40mV, the minimum hot swap load current is determined where the sense resistor is 3% high:
IHOT_SWAP (min) = 40mV 38.8mV = 1.03 x RSENSE (nom) RSENSE (nom)
Micrel
current, the controller's no-load detection loop is enabled. In this loop, an internal current source, ICNLD, will charge an external capacitor CNLD. An expression for the controller's no-load time-out delay is given by: C tNLD = VCNLD x NLD ICNLD where VCNLD = 1.24V (typ); ICNLD = 25A (typ); and CNLD is an external capacitor connected from Pin 6 to VEE. Once the voltage on CNLD reaches its no-load threshold voltage, VCNLD, the loop times out and the controller will shut down until it is reset manually (MIC2589/95) or until it performs an auto-retry operation (MIC2589R/95R). Undervoltage/Overvoltage Detection (MIC2589 and MIC2589R) The MIC2589 and the MIC2589R have "UV" and "OV" input pins that can be used to detect input supply rail undervoltage and overvoltage conditions. Undervoltage lockout prevents energizing the load until the supply input is stable and within tolerance. In a similar fashion, overvoltage turnoff prevents damage to sensitive circuit components should the input voltage exceed normal operational limits. Each of these pins is internally connected to analog comparators with 20mV of hysteresis. When the UV pin falls below its VUVL threshold or the OV pin is above its VOVH threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until the UV pin is above its VUVH threshold or the OV pin is below its VOVL threshold. The circuit's UV and OV threshold voltage levels are programmed using the resistor divider R1, R2, and R3 as shown in the "Typical Application " where the equations to set the trip points are shown below. For the following example, the circuit's UV threshold is set to VUV = 37V and the OV threshold is set at VOV = 72V, values commonly used in Central Office power distribution applications. VUV = VUVL (typ) x
Keep in mind that the minimum hot swap load current should be greater than the application circuit's upper steady-state load current boundary. Once the lower value of RSENSE has been calculated, it is good practice to check the maximum hot swap load current (IHOT_SWAP(max)) which the circuit may let pass in the case of tolerance build-up in the opposite direction. Here, the worst-case maximum is found using a VTRIP(max) of 60mV and a sense resistor 3% low in value:
IHOT_SWAP (max) = 60mV 61.9mV = 0.97 x RSENSE (nom) RSENSE (nom)
In this case, the application circuit must be sturdy enough to operate over an ~1.6-to-1 range in hot swap load currents. For example, if an MIC2595 circuit must pass a minimum hot swap load current of 4A without nuisance trips, RSENSE 38.8mV = 9.7m , and the nearest 1% 4A standard value is 9.76m. At the other tolerance extremes, IHOT_SWAP(max) for the circuit in question is then simply: should be set to 61.9mV = 6.3A 9.76m With a knowledge of the application circuit's maximum hot swap load current, the power dissipation rating of the sense resistor can be determined using P = I2 x R. Here, The I is IHOT_SWAP(max) = 6.3A and the R is RSENSE(min) = (0.97)(RSENSE(nom)) = 9.47m. Thus, the sense resistor's maximum power dissipation is: PMAX = (6.3A)2 x (9.47m) = 0.376W A 0.5 sense resistor is a good choice in this application. No-Load Detection For those applications in which a minimum load current will always be present, the no-load detect capability of the MIC2589/89R/95/95R family offers system designer the ability to perform a shutdown operation on such fault conditions, such as an unscheduled or unexpected removal of PC boards from the system or on-board fuse failure. As long as the minimum current drawn by the load is at least IHOT_SWAP (max) =
(R1+ R2 + R3) (R2 + R3) (R1+ R2 + R3)
R3
VOV = VOVH (typ) x
Given VUV, VOV, and any one resistor value, the remaining two resistor values can be determined. A suggested value for R3 is that which will provide approximately 100A of current through the voltage divider chain at VDD = VUV. This yields the following as a starting point: R3 = VOVH (typ) 100A = 1.223V = 12.23k 100A
The closest standard 1% value for R3 = 12.4k. Solving for R2 and R1 yields:
VTRIP 20% of the maximum output current (defined by R ), SENSE the output of the hot swap controllers will remain enabled. If the output current falls below 12% of the maximum output
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V R2 = R3 x OV - 1 VUV 72V R2 = 12.4k x - 1 = 11.73k 37V The closest standard 1% values for R2 = 11.8k. Lastly, the value for R1 is calculated:
VOV - 1.223V R1= R3 x 1.223V
Micrel
VON = VONH (typ) x
(R1+ R2 + R3)
R3
VOFF = VOFFL (typ) x
(R1+ R2 + R3)
R2 + R3
(
) - R2

Given VOFF, VON, and any one resistor value, the remaining two resistor values can be readily determined. A suggested value for R3 is that which will provide approximately 100A of current through the voltage divider chain at VDD = VOFF. This yields the following as a starting point: R3 = VOFFL (typ) 100A = 1.223V = 12.23k 100A
(72V - 1.223V) R1= 12.4k x - R2 1.223V R1= 705.81k
The closest standard 1% value for R3 = 12.4k. Solving for R2 and R1 yields: V R2 = R3 x ON - 1 VOFF 40V R2 = 12.4k x - 1 = 1.77k 35V The closest standard 1% value for R2 = 1.78 k. Lastly, the value for R1 is calculated: R1= R3 x
The closest standard 1% value for R1 = 698k. Using standard 1% resistor values, the circuit's nominal UV and OV thresholds are: VUV = 36.5V VOV = 71.2V Programmable UVLO Hysteresis (MIC2595 and MIC2595R) The MIC2595 and the MIC2595R devices have user-programmable hysteresis by means of the ON and OFF pins (Pins 4 and 3, respectively). This allows setting the MIC2595/95R to turn on at a voltage V1, and not turn off until a second voltage V2, where V2 < V1. This can significantly simplify dealing with source impedances in the supply buss while at the same time increasing the amount of available operating time from a loosely regulated power rail (for example, a battery supply). The MIC2595/95R holds the output off until the voltage at the ON pin is above its VONH threshold value given in the "Electrical Characteristics" table. Once the output has been enabled by the ON pin, it will remain on until the voltage at the OFF pin falls below its respective VOFFL threshold value, or the part turns off due to an external fault condition. Should either event occur, the GATE pin is immediately pulled low and will remain low until the ON pin voltage once again above its VONH threshold. The circuit's turn-on and turn-off voltage levels are set using the resistor divider R1, R2, and R3 as shown in the "Typical Application" where the equations to set the trip points are shown below. For the following example, the circuit's ON threshold is set to VON = 40V and the circuit's OFF threshold is set to VOFF = 35V.
(VON - 1.223V) - R2
1.223V
R1= 12.4k x
(40V - 1.223V) - R2
1.223V
R1 = 391.38k The closest standard 1% value for R1 = 392k. Using standard 1% resistor values, the circuit's nominal ON and OFF thresholds are: VON = 40.1V VOFF = 35V
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this will damage the transistor. However, the actual avalanche voltage is unknown; all that can be guaranteed is that it will be greater than the VBD(DS) of the MOSFET. The drain of the transistor is connected to the DRAIN pin of the MIC2589/95, and the resulting transient does have enough voltage and energy and can damage this, or any, high-voltage hot swap controller. 2. If the load's bypass capacitance (for example, the input filter capacitors for a set of DC-DC converter modules) are on a board from which the board with the MIC2589/95 and the MOSFET can be unplugged, the same type of inductive transient damage can occur to the MIC2589/95. Protecting the controller and the power MOSFET from damage against these large-scale transients can take the forms shown in Figure 8. It is not mandatory that these techniques are used - the application environment will dictate suitability. As protection against sudden on-card load dumps at the DRAIN pin of the controller, a 2.2F or larger capacitor directly from DRAIN to VEE of the controller can be used to serve as a charge reservoir. Alternatively, a 68V, 1W, 5% Zener diode clamp can be installed in a similar fashion. Note that the clamp diode's cathode is connected to the DRAIN pin as shown in Figure 8. To protect the hot swap controller from large-scale transients at the card input, a 100V clamp diode (an SMAT70A or equivalent) can be used. In either case, the lead lengths should be short and the layout compact to prevent unwanted transients in the protection circuit. [Circuit drawing under construction] Figure 8. Using Large-Scale Transient Protection Devices Around the MIC2589/95 and the MIC2589R/95R The same logic applies to the input of the MIC2589/95 circuit. Power bus inductance could easily result in localized highvoltage transients during a turn-off event. The potential for overstressing the part in such a case should be kept in check with a suitable input capacitor and/or transient clamping diode. Power MOSFET Selection [Section under construction] Power MOSFET Operating Voltage Requirements [Section under construction] Power MOSFET Steady-State Thermal Issues [Section under construction] Power MOSFET Transient Thermal Issues [Section under construction] PCB Layout Considerations [Section under construction]
Applications Information
4-Wire Kelvin Sensing Because of the low value typically required for the sense resistor, special care must be used to measure accurately the voltage drop across it. Specifically, the measurement technique across RSENSE must employ 4-wire Kelvin sensing. This is simply a means of ensuring that any voltage drops in the power traces connected to the resistors are not picked up by the signal conductors measuring the voltages across the sense resistors. Figure 7 illustrates how to implement 4-wire Kelvin sensing. As the figure shows, all the high current in the circuit (from VEE through RSENSE and then to the source of the output MOSFET) flows directly through the power PCB traces and through RSENSE. The voltage drop across RSENSE is sampled in such a way that the high currents through the power traces will not introduce any parasitic voltage drops in the sense leads. It is recommended to connect the hot swap controller's sense leads directly to the sense resistor's metalized contact pads.
RSENSE metalized contact pads
Power Trace From VEE PCB Track Width: 0.03" per Ampere using 1oz. Cu Signal Trace to MIC2589/95 VEE Pin
RSENSE
Power Trace To MOSFET Source
Signal Trace to MIC2589/95 SENSE Pin
Note: Each SENSE lead trace shall be balanced for best performance -- equal length/equal aspect ratio.
Figure 7. 4-Wire Kelvin Sense Connections for RSENSE Protection Against Voltage Transients In many telecom applications, it is very common for circuit boards to encounter large-scale supply-voltage transients in backplane environments. Because backplanes present a complex impedance environment, these transients can be as high as 2.5 times steady-state levels, or 120V in worst-case situations. In addition, a sudden load dump anywhere on the circuit card can generate a very high voltage spike at the drain of the output MOSFET which, in turn, will appear at the DRAIN pin of the MIC2589/95. In both cases, it is good engineering practice to include protective measures to avoid damaging sensitive ICs or the hot swap controller from these large-scale transients. Two typical scenarios in which largescale transients occur are described below: 1. An output current load dump with no bypass (charge bucket or bulk) capacitance to VEE. For example, if LLOAD = 5H, VIN = 56V and tOFF = 0.7s, the resulting peak short-circuit current prior to the MOSFET turning off would reach:
(55V x 0.7s) = 7.7A
5H
If there is no other path for this current to take when the MOSFET turns off, it will avalanche the drainsource junction of the MOSFET. Since the total energy represented is small relative to the sturdiness of modern power MOSFETs, it's unlikely that March 2004 15
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Power MOSFET and Sense Resistor Vendors Table 1 shows some of the various sense resistor types available for use with the MIC2589/95 product family. Resistor Vendors Vishay (Dale) IRC Contact Data www.vishay.com/docs/wsl_30100.pdf (203)452-5664 "OARS" Series www.irctt.com/pdf_files/OARS.pdf "LR" Series www.irctt.com/pdf_files/LRC.pdf (second source to "WSL") (828) 264-8861 Table 1. Suggested Sense Resistors Resistor Types "WSL" Series
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Package Information
PIN 1
0.154 (3.90)
DIMENSIONS: INCHES (MM)
0.026 (0.65) MAX)
0.050 (1.27) 0.016 (0.40) TYP TYP 0.006 (0.15)
0.193 (4.90) 45 3-6 0.244 (6.20) 0.228 (5.80)
0.057 (1.45) 0.049 (1.25)
0.344 (8.75) 0.337 (8.55)
SEATING PLANE
14-Pin SOIC (M)
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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